Field of the Invention
The present invention relates to an electronic circuit package and, more particularly, to an electronic circuit package using a composite magnetic sealing material.
Description of Related Art
In recent years, an electronic device such as a smartphone is equipped with a high-performance radio communication circuit and a high-performance digital chip, and an operating frequency of a semiconductor IC used therein tends to increase. Further, adoption of an SIP (System-In Package) having a 2.5D or 3D structure, in which a plurality of semiconductor ICs are connected by a shortest wiring, is accelerated, and modularization of a power supply system is expected to accelerate. Further, an electronic circuit module having a large number of modulated electronic components (collective term of components, such as passive components (an inductor, a capacitor, a resistor, a filter, etc.), active components (a transistor, a diode, etc.), integrated circuit components (an semiconductor IC, etc.) and other components required for electronic circuit configuration) is expected to become more and more popular, and an electronic circuit package which is a collective term for the above SIP, electronic circuit module, and the like tends to be mounted in high density along with sophistication, miniaturization, and thinning of an electronic device such as a smartphone. However, this tendency poses a problem of malfunction and radio disturbance due to noise. The problem of malfunction and radio disturbance is difficult to be solved by conventional noise countermeasure techniques. Thus, recently, self-shielding of the electronic circuit package has become accelerated, and an electromagnetic shielding using a conductive paste or a plating or sputtering method has been proposed and put into practical use, and higher shielding characteristics are required in the future.
To achieve this, recently, there are proposed electronic circuit packages in which a molding material itself has magnetic shielding characteristics. For example, Japanese Patent Application Laid-Open No. H10-64714 discloses a composite magnetic sealing material added with soft magnetic powder having an oxide film as a molding material for electronic circuit package.
However, conventional composite magnetic sealing materials have a drawback in that it has a large thermal expansion coefficient. Thus, a mismatch occurs between a composite magnetic sealing material and a package substrate or electronic components in terms of the thermal expansion coefficient. As a result, an aggregated substrate having a strip shape after molding may be greatly warped, or there may occur a warp large enough to cause a problem with connectivity of an electronic circuit package in a diced state in mounting reflow. This phenomenon will be described in detail below.
In recent years, various structures have been proposed for and actually put into practical use as a semiconductor package or an electronic component module, and, currently, there is generally adopted a structure in which electronic components such as semiconductor ICs are mounted on an organic multilayer substrate, followed by molding of the upper portion and periphery of the electronic component package by a resin sealing material. A semiconductor package or electronic component module having such a structure is molded as an aggregated substrate, followed by dicing.
In this structure, an organic multilayer substrate and a resin sealing material having different physical properties constitute a so-called bimetal, so that a warp may occur due to the difference between thermal expansion coefficients, glass transition, or curing shrinkage of a molding material. To suppress the warp, it is necessary to make the physical properties such as thermal expansion coefficients coincide with each other as much as possible. In recent years, an organic multilayer substrate used for a semiconductor package or an electronic circuit module is getting thinner and thinner and is increasing in the number of layers thereof to meet requirements for height reduction. In order to realize high rigidity and low thermal expansion for ensuring good handleability of a thin substrate while achieving the thickness reduction and multilayer structure, use of a substrate material having a high glass transition temperature, addition of a filler having a small thermal expansion coefficient to a substrate material, or use of glass cloth having a smaller thermal expansion coefficient is a common practice at present.
On the other hand, the difference in physical properties between semiconductor ICs and electronic components mounted on a substrate and a molding material also generates a stress, causing various problems such as interfacial delamination of the molding material and crack of the electronic components or molding material. Incidentally, silicon is used as the semiconductor ICs. The thermal expansion coefficient of silicon is 3.5 ppm/° C., and that of a baked chip component such as a ceramic capacitor or an inductor is about 10 ppm/° C.
Thus, the molding material is also required to have a small thermal expansion coefficient, and some commercially-available materials have a thermal expansion coefficient below 10 ppm/° C. As a method for reducing the thermal expansion coefficient of the molding material, adopting an epoxy resin having a small thermal expansion coefficient, as well as, blending fused silica having a very small thermal expansion coefficient of 0.5 ppm/° C. in a sealing resin at a high filling rate can be taken.
General magnetic materials have a high thermal expansion coefficient. Thus, as described in Japanese Patent Application Laid-Open No. H10-64714, the composite magnetic sealing material obtained by adding general soft magnetic powder to a mold resin cannot achieve a target small thermal expansion coefficient.
Japanese Patent Application Laid-Open No. S59-132196 discloses an electronic circuit package whose shielding characteristics are enhanced by molding an electronic circuit using a magnetic mold resin and covering the entire structure with a metal casing.
However, in the electronic circuit package disclosed in Japanese Patent Application Laid-Open No. S59-132196, the covering of the entire structure with the metal casing makes reduction in height difficult. Further, the metal casing has a large number of holes formed therein and is not connected to a ground pattern of a substrate, so that a sufficient shielding effect cannot be obtained.